Tutorials
SOCC 2017 Tutorial Day Program
September 5, 2017
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7:30AM – 10:00AM |
Registration |
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9:00AM – 10:30AM |
T1A |
T1B Propelling Breakthrough Embedded Microprocessors by Means of Integrated Photonics |
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10:30AM – 10:45AM |
Coffee break |
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10:45AM – 12:15PM |
T2A |
T2B Globalfoundries
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12:15PM – 2:00PM |
Lunch break |
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2:00PM – 3:30PM |
T3A |
T3B
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3:30PM – 3:45PM |
Coffee break |
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3:45PM – 5:15PM |
T4A Dr. Robert Wille Design Automation for Labs-on-Chip: A New "Playground" for SoC Designers |
T4B Dr. Andrew Marshall, The Importance of Benchmarking for charge-based and Beyond CMOS Devices |
Time Sensitive Networks for Industry 4.0
Thomas Leyrer, System Application Manager, Texas Instruments, Freising, Germany
Abstract: The digital revolution in manufacturing process demand a communication standard which meets the requirements of the manufacturing floor. Additional sensing technology for predictive maintenance add new quality of service requirements to the industrial network. Managing different communication requirements for motion control, programmable logic control and predictive maintenance is the key challenge of applying IEEE Time Sensitive Network (TSN) standard to the trends in industrial automation market.
This session discusses the characteristic of a manufacturing system built of machine tool with predictive maintenance and a handling robot with camera based safety monitor. The communication requirements of various applications in this system are mapped to TSN standard modules listed under IEEE 802.1 and IEEE 802.3. It provides a configuration example to combine the various stream classes into a profile for TSN which meets the requirement of modern production cells.
Second part of the session covers the semiconductor requirements to support deterministic, low latency and min jitter networked IO system. The physical layer in industrial environment needs to ensure error free transmission of the packet based communication. Different physical layer technologies with TSN communication support a single network technology for the various subsystems. The integration of TSN switching layer into embedded processors is a key element to ensure the quality of service of TSN up to application layer. Time synchronization aspects for network clock and application clock are discussed in the context of a production cell.
Last part of the session compares current fieldbus and industrial Ethernet technologies with the industrial profile example of TSN. It gives an outlook of semiconductor trends which enable TSN into PLC backplane and industrial sensor networks.
Biography: Thomas Leyrer is System Architect of TIs Industrial Communication solutions. He is responsible to develop solutions for Industrial Automation market including Fieldbus and Industrial Ethernet on TI Embedded Processors.
Thomas has more than 25 years experience with TI’s Semiconductor Group. He held several engineering and application manager positions for Computer, Automotive, Broadband Communication and Industrial Automation market. He is an advocate of Linux Open Source and system architect for industrial communication on ARM SoCs.
Thomas holds an Engineering degree in Electrical Engineering from FH Landshut.
Low Power Circuit Optimization for IoT
Dr. Michael Pronath, Vice President Products, Solutions & Support, MunEDA GmbH
Abstract: Designing circuits for enhanced IoT („Internet of Things“) applications is one of the current growth driver for the electronics industry. Optimizing such circuits for lowest power consumption while maximize functionality and performance is key for successful implementation of such circuits in the IoT systems. IoT devices are diverse in nature but are typically constrained by limited power availability, limited area budget and the need for modularity of design. The burden of ultra-low-power budget unfortunately doesn't necessarily mean that other performance requirements are relaxed. The tutorial is therefore geared towards designers of IoT devices including sensors, MEMS, mobile devices, medical sensors, wireless communication devices, near field communication devices, energy harvesting designs, mobile devices, and wireless communication devices. It will focus on how automated circuit sizing and tuning methodologies can be used to enhance existing design expertise to reduce power consumption while trade-off with other circuit performances. Additionally it will be shown how features like circuit sensitivity analysis can be used for confirming design hypotheses. Using such a verification and optimization environment can help systematically and fully explore design's operating, design and statistical design space.
Biography: Michael Pronath has co-founded the international established EDA Software Provider MunEDA in 2002 and is since running the company as MunEDA’s Vice President Products, Solutions & Support. Prior to co-founding MunEDA, After graduating with a Diplom-Ingenieur from Munich Technical University (TUM) Michael worked as a research assistant at the TUM Institute for Electronic Design Automation. He holds a Diploma and PhD in Electrical Engineering from Munich Technical University as well as a MBA degree from University of Hagen. Michael has extensive experience in statistical analysis and modeling techniques for circuit design. Furthermore he is well known expert in methodologies for circuit level design optimization and improvement. Dr. Pronath is author and coauthor of more than 50 international papers and publications about methods of analog integrated circuit design and testing of mixed-signal circuits at international conferences such as DAC, DATE, ISQED, IP-ESC, ZuE, DASS, SBCCI, ICCAD, CICC, IRPS, and many more. He also is co-author of 2009 IEEE Transactions paper about „Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas“.
T3A (Room: Tegernsee)
Reliability for IoT and Automotive markets
Subhadeep Ghosh, Lead Engineer, Texas Instruments, India
Scott Martin, Shane Stelmach, Texas Instruments, USA
Abstract: The semiconductor industry is strategically focusing on automotive and industrial markets. Significant investment is targeted to address these markets. The automotive industry in particular is already in focus for last several years. At the same time, with its seemingly endless possibilities in the “internet of things” (IOT) world, industrial markets are gaining attention as building automation, factory automation, and grid infrastructure rapidly advance.
For the newer markets, reliability is emerging as a key metric in semiconductor design along with the traditional cost, power, and performance considerations. While developing reliable devices is a prerequisite for TI and any other company, demonstrating long term reliability is difficult as industry standards are inadequate. One reason is that the standards, such as JEDEC, AEC-Q100, ASIL focus on quality, qualification tests, or safety, but are insufficient to predict end-of-life (EOL) reliability. Historically reliability has been managed by transistor and wire (component) reliability data provided by the manufacturing site; subsequently design restrictions in voltage, current density, and circuit timing margins are implemented and devices were designed based on these single-component restrictions. This approach has served the industry well as the industry has proven capable of producing low DPPM parts; however, we’ve reached the point where the industry has complicated SOCs, consisting of many subsystems: processors that are often multicore; measurement and sensor modules; power management macros; and various peripherals. As we scale to higher-reliability automotive and industrial markets, it would be ideal to have a set of metrics to identify key failure modes and compute their failure rates. Specifically, this requires standardization in the EDA community to incorporate failure models and also IP providers to utilize the failure models and publish failure rates that are sufficiently low to support these markets.
The cost of not ensuring product reliability is very costly, especially for the automotive and industrial markets, due to failed parts, customer returns, root-cause, and identification of corrective and preventive actions. The gap the industry is presently facing is how we understand, measure and address reliability for advanced SOCs. The existing guidelines cannot predict the product failure rates accurately. While devices have a proven record of meeting existing DPPM requirements, with the advancing quality and reliability in automotive and industrial markets, the existing EDA solutions are inadequate to quantify reliability. A systematic and coherent approach is needed across the industry, including: manufacturing, IP providers, EDA solutions, and SoC designers. The “Design-In-Reliability” philosophy could be used to solve specific reliability concerns for these demanding markets.
Biography: Subhadeep Ghosh leads the design reliability and IR-drop signoff activities in the Backplane team of the Embedded Microcontrollers Silicon Development at Texas Instruments. He has been with TI for more 12 years with expertise on design reliability analysis covering transistor and interconnect reliability. His areas of interest are design reliability analysis for Gate Oxide Integrity, Electromigration and ESD/Latch-up. Over the last few years, he has also been working on IR-drop integrity analysis for low-power, macro-heavy microcontroller designs. Subhadeep holds a bachelor’s degree in Electronics Engineering from Jadavpur University, Kolkata, India and a master’s degree from Indian Institute of Technology, Kharagpur, India.
Biography: Scott Martin received a Ph.D in physical chemistry from the University of Notre Dame. He has worked at Texas Instruments since 1998, where he worked in developing TI’s copper / Low-K interconnect technology, and later on developing TI’s FRAM nonvolatile memory technology. Since 2008, he’s worked as Quality and Reliability engineer covering qualification and product reliability. More recently, his efforts have focused on design reliability for advanced CMOS technologies that target automotive and industrial markets.
Biography: Shane Stelmach is a Senior Member of the Texas Instruments Technical Staff. He currently is responsible for all aspects of Power and Reliability in Embedded Processors Silicon Development. He is responsible for RTL-to-tape-out implementation and verification of power management and power integrity as well as reliability signoff. He has previously has worked in circuit design, IP development, chip-package co-design and EDA development. He is a graduate of Texas A&M University.
Design Automation for Labs-on-Chip: A New "Playground" for SoC Designers
Dr. Robert Wille, Johannes Kepler University, Linz, Austria
Dr. Bing Li, Technical University of Munich, Germany
Abstract: In the recent years, microfluidic technology has paved the way for so-called Labs-on-Chips (LoCs) – a convenient and cost-effective way to conduct biochemical, biological, or medical experiments. Instead of conducting tests manually in a fully equipped lab using up lab equipment and human resources, LoCs allow us to conduct biochemical and medical experiments on a small chip. This requires much smaller sample/reagent volumes and allows for a significantly higher throughput.
At the same time, designing the corresponding chips has become a considerably complex task. State-of-the-art LoCs are comprised of thousands - even tens of thousands – of entities and a million features in order to conduct certain experiments with increasing tendency. Time to market constraints and fault tolerance considerations will further complicate the design. Despite the complexities, most of the LoCs are designed manually: Engineers draw the designs for corresponding devices by hand – a costly and time-consuming process.
In this tutorial, we provide an overview on different LoC technologies (including electrowetting-based and flow-based LoCs as well as solutions based on two-phase microfluidics) as well as the corresponding design tasks. Afterwards, we sketch how to tackle the resulting challenges by design automation. By this, attendees of the tutorial will get introduced into a new application area where System-on-Chips play a major role to employ the respective laboratory experiments on an LoC as well as to control the biochemical actions.
Biography: Robert Wille received the Diploma and Dr.-Ing. degrees in computer science from the University of Bremen, Germany, in 2006 and 2009, respectively. He has been with the Group of Computer Architecture, University of Bremen, Germany, from 2006-2015 and with the German Research Center for Artificial Intelligence (DFKI), Bremen, Germany, from 2013 onwards. Additionally, he worked as lecturer at the University of Applied Science of Bremen, Germany, and as Visiting Professor at the University of Potsdam, Germany, and the Technical University Dresden, Germany. Since 2015, he is Full Professor at the Johannes Kepler University Linz, Austria. His research interests are in the design of circuits and systems for both conventional and emerging technologies. In the ten years of his research activity, he published more than 140 papers in journals and conferences and served in program committees of numerous conferences such as ASP-DAC, DAC, and ICCAD.
Biography: Bing Li received the bachelor’s and master’s degrees in communication and information engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 2000 and 2003, respectively, and the Dr.-Ing. degree in electrical engineering from Technical University of Munich (TUM), Munich, Germany, in 2010. He is currently a researcher with the Institute for Electronic Design Automation, TUM. His research interests include high-performance and lower-power design, as well as emerging systems. He has served in program committees of several conferences such as ASP-DAC, ICCAD, DATE.
Propelling Breakthrough Embedded Microprocessors by Means of Integrated Photonics
Dr. Davide Bertozzi, University of Ferrara, Italy
Dr. Sébastien Rumley, Columbia University, New York, USA
Abstract: The tutorial aims to address electrical communications link limitations by developing chip-scale, integrated photonic technology to enable seamless intrachip and off-chip photonic communications that provide the required bandwidth with low energy/bit. The emerging technology will exploit wavelength division multiplexing (WDM), allowing much higher bandwidth capacity per link, which is imperative to meeting the communication needs of future microprocessors. Such a capability would propel the microprocessor onto a new performance trajectory and impact the actual runtime performance of relevant computing tasks for power-starved embedded applications and supercomputing. The challenges in realizing optical interconnect technology are developing CMOS and DRAM-compatible photonic links that are spectrally broad, operate at high bit-rates with very low power dissipation, and are tightly integrated with electronic drivers.
Ultimately, the goal of this tutorial is to demonstrate photonic technologies that can be integrated within embedded microprocessors and enable seamless, energy-efficient, high-capacity communications within and between the microprocessor and DRAM. It is envisioned that optical interconnect technology will be especially useful for those platforms where extreme performance coupled with low size, weight, and power is a necessity (e.g. UAVs, and satellites).
Biography: Davide Bertozzi received the PhD degree in Electrical Engineering from University of Bologna in 2003. Since 2005, he is Assistant Professor at University of Ferrara and leads the Multi-Processor System-on-Chip Design group. He was a Visiting Researcher at International Academic Institutions (Stanford University, USA) and Semiconductor Industries (NEC America Labs, USA; NXP Semiconductors, Holland; STMicroelectronics, Italy; Samsung Electronics, Korea). His main research interests concern MPSoC design issues, with emphasis on the communication architecture and on its evolution to an on-chip network. His studies address mainly power and reliability concerns, which are tackled by means of architecture as well as circuit level techniques with layout awareness. He has been program chair of recent events of the network-on-chip community (Int. Symposium on Networsk-on-Chip 2008, IET CDT Special Issue on NoCs 2009). He takes part to the technical program committee of international conferences (e.g., Design and Automation Conference, Int. GLSVLSI Symposium, Int.Symp. on Networks-on-Chip) and scientific journals (IEEE Transactions on VLSI, on CAD of Circuits and Systems, on Computers). He is member of the Editorial Board of the IET Computers and Digital Techniques Journal.
He is involved in the Galaxy FP7 project studying the applicability of the GALS paradigm to NoCs, and in the Hipeac-2 Network-of-Excellence, where he is involved with the activities of the Interconnect Cluster.
Biography: Sébastien Rumley received the M.S. degree in communication systems and the PhD degree in computer and communication sciences, both from Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He is currently an Associate Research Scientist in the Department of Electrical Engineering, Columbia University in the City of New York, NY, USA. His research focuses on optical interconnect modeling, mainly for applications in High-Performance Computing and Distributed Computing platforms.
T2B (Room: Chiemsee)
FDSOI Design Experience and Recommendations
Herbert Preuthen, Jürgen Dirks, GLOBALFOUNDRIES
Abstract: 22FDX™ is new technology from GLOBALFOUNDRIES based on Fully-Depleted-Silicon-on-Insulator (FDSOI). Its transistor architecture consists of a thin layer of semiconductor material on top of a body-oxide. On the top side, a planar leading-edge MOS-transistor is formed. From the bottom, the wells have electrostatic influence through the body-oxide, which is large enough to shift the transistor threshold voltages between high-performance- and low-leakage-operation.
The tutorial will give an introduction to the technology and show the digital design reference flow from GLOBALFOUNDRIES, which has been developed for 22FDX. Particular emphasis will be given on how to use FDSOI for low-power designs using the back-gate bias. Also, design examples will be exposed and results will be discussed.
Biography: Herbert Preuthen is currently working as a Senior Member of Technical Staff at GLOBALFOUNDRIES in Munich supporting the implementation of 22FDSOI designs. He also worked on reference flow development and test chip implementation. Before GLOBALFOUNDRIES he was working at LSI as technical lead engineer responsible for the execution of customer ASIC projects and as physical design engineer at Toshiba.
Herbert holds a Master’s Degree from Aachen University, Germany.
Biography: Juergen Dirks received a Master's Degree in electrical engineering from the Technische Universitaet Braunschweig, Germany. After that he worked as SOC designer and customer ASIC engineer in various positions and locations with SICAN and LSI before joining GLOBALFOUNDRIES in 2013. Since then Juergen has worked on reference flow development, test chip implementations and customer design evaluations for advanced GLOBALFOUNDRIES technologies including 22FDSOI.
IBM Q - Introduction into Quantum Computing with live demo
Dr. Albert Frisch, IBM Germany Research & Development, Böblingen, Germany
Abstract: In a press release on March 6th 2017, IBM has commited itself to develop a commercial quantum system called IBM Q. For the first time this enables IBM to directly target potential customers in this field e.g. HPC groups or industrial R&D departments. Early access to a Quantum Computer on the cloud is enabled via the IBM Quantum Experience. The IBM Quantum Computer has been presented at this years CeBIT in Hannover.
The great advantage of a universal Quantum Computer is based on quantum mechanical effects, which are not known in classical every-day life, e.g. superposition, entanglement, and teleportation. Using these effects in smart ways certain algorithms can be boosted beyond classical limits. But controlling and measuring qubits in large scales turns out to be a great challenge.
In my talk I will point out the fundamental differences between a classical computer and a quantum computer. I will show in detail how the IBM Quantum Computer works and what potential pitfalls are there for scaling quantum systems. In a live demo we will program simple quantum algorithms and execute them on the IBM quantum computer in real-time.
Biography: Albert Frisch received his PhD from the Institut of Experimental Physics in Innsbruck in 2014. His PhD work was awarded the thesis prize of the Institute for Quantum Optics and Quantum Information in the beginning of 2016. In June 2015 Albert Frisch joined the IBM lab as an Array Designer for P/Z processors in the Processor Physical Design department. As an expert for Quantum Computing he contributes in introducing this highly innovative field of research to the Boeblingen Lab.
T4B (Room: Chiemsee)
The Importance of Benchmarking for charge-based and Beyond CMOS Devices
Andrew Marshall, Research Professor, University of Texas, Dallas
Nishtha Sharma, University of Texas, Dallas
Abstract: As it has become physically more difficult and more expensive to extend the performance characteristics of planar CMOS technology, there have been many efforts to create new technologies. Some of these are CMOS extensions, such as Finfet devices. Others are the so-called beyond CMOS devices, which include charge-based logic such as Tunnel FET based systems, others are non-charge based, which include nano-magnetic structures, spintronics devices, advanced charge-based devices and a variety of quantum structures.
It is important to determine which of these device types offer advantages over conventional CMOS, and as a result there has been much investigation into comparative benchmarking of the technologies. We here detail benchmarking of CMOS and of newer beyond CMOS technologies, and how the benchmarking standards have been changed by the addition of beyond CMOS capability.
Biography: Andrew Marshall is an analog and digital IC design expert, working on benchmarking of leading edge and future technologies. He is a research professor at the University of Texas in Dallas. Dr. Marshall has authored/co-authored approximately 85 patents and 100 papers. He is co-author of the book ‘SOI Design: Analog, Memory and Digital Techniques’ and sole author of “Mismatch and Noise in Modern IC Processes”. Dr. Marshall is a Fellow of both the IEEE and Institute of Physics, and Fellow Emeritus of Texas Instruments Incorporated.
Biography: Nishtha Sharma is a Ph.D. candidate and research assistant at the department of Electrical Engineering (EE) at the University of Texas at Dallas (UTD). Her areas of interest are beyond CMOS logic and memory devices, including development of SPICE models for low-power, voltage-controlled Magnetic Tunnel Junctions (MTJ) that utilize novel magneto-electric materials as their switching components, and Ferro-electric memory devices. She has previously interned at ARM and GlobalFoundries. She completed her master’s degree in electrical engineering from University of Texas at Dallas in 2015.
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Distinguished Speakers
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JOSEF HAUSNER
Division Vice President R&D IP Strategy |
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JÖRG HENKELChair for Embedded Systems CES |
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RON MARTINO
Vice President |
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GERD TEEPE
Director Marketing for Europe, |
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NORBERT WEHN
Professor and Chair |
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...and more |
